The memory capacity of memory devices has significantly increased in recent years. Corresponding to this increase in memory capacity is a greater likelihood for memory devices to be manufactured with defective memory cells or for at least some memory cells of the memory device to become defective through use. Any defective memory cell in a memory device may, to varying degrees, negatively affect the operation of a computing device or other device that may employ the memory device for data storage.
Error correction schemes may be used to deal with single-bit errors or multi-bit errors resulting from memory defects that are detected during the operation of a computing system. Other schemes for handling memory errors detected during the operation of a computing system are also known.
For example, U.S. Pat. No. 7,694,195 describes a method of managing memory defects. Defective memory locations are detected in a scan operation during the startup of a computer system, and the memory defect information is stored in a memory defect map. Subsequently, these defective memory locations may be skipped during normal operating procedures.
U.S. Pat. No. 7,783,919 further describes detecting and handling memory errors during execution of a run time environment within a computer system. If it is determined that a memory error has occurred, memory locations on individual memory devices where the memory error occurred may be identified, and references to these memory locations can be stored in a persistent memory of a memory module. Moreover, U.S. Patent Publication No. 2010/0251044 discloses generating a memory map, wherein usable memory regions containing defective memory elements are excluded from the memory map.